The present invention relates to a semiconductor device, and more specifically to a capacitor and to a semiconductor device equipped with a capacitor.
Dynamic random, access memories (hereinafter referred to as DRAMs) have been realized in ever highly densely integrated form at a striking rate at all times. The main stream at the present time is constituted by 256-kilobit DRAMs. However mass production of 1-megabit DRAMs has been started already. The trend toward such high integration degrees is made possible chiefly by the reduction of dimensions of devices. Accompanying the reduction in the dimensions, however, the capacitor area decreases and the capacitance of a storage capacitor of the memory decreases causing the signal-to-noise ratio (S/N ratio) to decrease and giving rise to the occurrence of signal reversal (so-called soft error) due to .alpha.-rays, imposing a serious problem from the standpoint of reliability. Therefore, it has heretofore been attempted to reduce the thickness of the capacitor insulator in order to prevent the reduction of capacitance that stems from the decrease in the dimensions. In the case of the 1-megabit DRAM, the thickness is 10 nm in terms of silicon dioxide equivalent. In the case of the 4-megabit DRAM of the next generation, it is considered that the thickness of the insulator must be reduced to 4 to 6 nm. The thickness of the capacitor insulator in terms of silicon dioxide equivalent is that of a silicon dioxide film formed by thermal oxidation composing the capacitor with the same capacitance, and is expressed by the following formula, i.e., ##EQU1## where C denotes a measured capacitance S denotes an area, .epsilon. denotes a dielectric constant of SiO.sub.2 formed by the thermal oxidation, and d denotes a thickness of the film converted into the silicon dioxide film.
As the thickness of the insulator becomes so small, however, a tunnel current flows through the insulator of the capacitor and the stored charge is lost. This fact has been discussed for example, in Solid-State Electronics, Vol. 10, 1967, pp. 865-873.
One of means for solving this problem is represented by a capacitor called tacked capacitor in which electrodes and an insulator are stacked on the gate of a drive MOS transistor and on a thick insulator for device isolation. The stacked capacitor has been disclosed, for example, in Japanese Patent Publication No. 55258/1986. In the stacked capacitor as described above, a portion thereof is formed so as in to be stacked on the MOS transistor or on the insulator for device isolation enabling the capacitor area to be increased. Therefore, even when an insulator is used having a thickness of 10 nm in terms of silicon dioxide equivalent, it becomes possible to maintain a capacitance required for the 4-megabit DRAM. Namely, the problem of extinction of the stored charge is solved.
With the above-mentioned prior art, however, it is no longer possible to further increase the degree of integration. In order to realize, for instance, a 16-megabit dynamic random access memory (DRAM), the thickness of the capacitor insulator must be further decreased. As the thickness of the insulator is decreased to about 5 nm in terms of silicon dioxide equivalent, however, the problem arises again, i.e., the stored charge are lost because of the resulting tunnel current. It has been reported also that the insulator 5 nm thick barely meets the needs for practical application. However, it becomes quite difficult to further decrease the thickness. When the DRAM is integrated to an even higher degree, furthermore, the throughput may decrease due to variation in the thickness of the capacitor insulator; i.e., it is virtually impossible to further increase the degree of integration.